Time Triggered Ethernet Core

Time-triggered Ethernet (TTE) standard has been deployed in aircraft and spacecraft applications - well proven. From flight control to time-critical sensor applications, TTE is highly versatile and trusted to operate mission critical, high reliability applications including aerospace. TTE differs from regular Ethernet as it delivers data reliably and on-time - important for safety, deterministic applications. Organizations like NASA, ESA, Boeing, Airbus and others use TTE for their aerospace projects due to its ability to self-stabilize as well as help devices to maintain time synchronization and fault-tolerant (continue to function in the event of failure). TTE has been integrated in both civil and government aerospace systems. LeWiz has been working with customers to develop TTE technologies for use in aerospace. LeWiz TTE IP Core is a part of LeWiz comprehensive TTE solutions.

Using Time-Triggered Ethernet, the core performs time synchronization, time triggered traffic transmit and receive, and supports rate-controlled traffic/best-effort Ethernet traffic to provide users with reliable and fault-tolerant network. The core can be used for endpoint and switching systems. It has a configurable number of virtual links (VLs), each with a high timing accuracy, and monitors incoming traffic for meeting VL timing windows. The TTE core uses LeWiz Timing Engine which provides precision timing and had been production deployed in other timecritical applications.

For user interface, the TTE core provides an AXI-stream bridge and PHY interface. The AXI-stream bridge provides AXI-stream (AXIS) bus to connect to user internal bus. AXIS is well-known, fast and easy to use. The PHY interface facilitates a connection between the TTE core and external PHY via standard PHY protocols such as *GMII supporting up to 10Gbps or higher.

The TTE core is available with design examples, verification bench, documentation, and software. Due to the core's use of the common, well known standard protocols, the TTE Core is easy to integrate into the user's design environment and test. It can be licensed for designs, testing, production, and deployment.

Features

• Applicable for endpoint or switching systems
• Time sync protocol control frame (PCF) traffic handling without software assist for low latency
• Supports 4 traffic types on a network: PCF, time-triggered (TT), rate controlled, best effort
• Configurable number of virtual links
• Extensive tracking of TX/RX data, statistics and conditions - useful in network debug, optimization
• Verification bench: capable of using data from standard network tools or lab captured
• hardware timestamping
• 64-bit AXI4 Stream for user bus interface
• Supports DMA to minimize CPU requirements
• Host and TT Core clocks can run at different frequencies - easy user meeting design timing
• ARINC 664-p7 compatible
• Applicable for FPGA or ASIC implementation
• Support deep nano-meter silicon process (12nm)
• Polling and interrupt mechanisms
• Hardware based packet transmission - accurate timing
• Fine grain timer with macrotick
• Independent priority queues
• Packet validity check
• Arrival window checking per virtual link
• 1Gbps, 10Gbps, or higher
• Complete test bench
• Emulators available for easy development
• AXIS master emulator
• PHY/network emulator: Gbps PHY + network functions

See datasheet for more information.