AXI-Lite I2C Controller Core

Inter-Integrated Circuit or I2C is a widely used protocol, popular for bidirectional communication between master and low speed peripherals. The I2C interface allows for bi-directional communication with multiple slave devices from a master device. Its advantages include low-power and require very few pins - 2 pins. Its interface is integrated into many sensors such as temperature sensors, accelerometers, gyroscopes, fans, bridging chips, EEPROMs, flash memory, FPGAs, CPLDs, GPIO expanders and many more.

LeWiz AXI-Lite I2C Controller (Controller) incorporates I2C interface for connecting to the I2C slave devices. It has a 32-bit AXI-Lite (AXIL) interface to facilitate communication between the AXIL bus master and the AXIL I2C Controller. Control of the AXIL I2C Controller is via its registers - simple for software to use. Its registers are used for functions such as holding configuration/control, status information and necessary for data exchange. The registers are each 32-bits wide and divided into 4 groups:

• The Write Data Register Group holds written data (up to 8 bytes) from the AXIL interface that is eventually used for transmitting out of the I2C bus by the Controller. This group has 2 registers to contain the upper and lower 32 bits of the transmitting data. Software writes to these registers for transmitting data out.
• The Read Data Register Group holds the data read from the external I2C device (up to 8 bytes per read). There are 2 32-bit registers holding the upper and lower parts of the up-to-8-byte data. Software read out the data from these registers for each I2C cycle.
• The Write/Read Address/Control Register Group contains the I2C device address, write/read cycle control information. It also contains the status of the I2C operations and specifies the number of data bytes performed.
• The Time Related Group defines timing characters of the I2C operations including controlling timings of the SCL and SDA signals as well as the frequency and duty cycle of the SCL clock signal.

The Controller core is available. It also has a test bench, test vectors, documents, design examples, and space-capable version. The I2C core can be integrated in user design environment through AXIL bus. AXIL is well-known and simple to use.

Features

• Uses simple AXI-Lite Interface - VALID/READY handshake mechanism
• Facilitates communication between AXIL bus master and I2C slave device(s)
• Supports simple single transfer - up to 8 bytes per transfer
• 16 registers (32 bits wide, divided into 4 groups)
• Simple control, status, data mechanism
• Efficient address decoding, state machine control, and data buffering
• Bidirectional I2C bus
• Can be used with FPGA or ASIC development
• Compatibility with a wide range of I2C devices and simulation models.
• Available for rad-hard applications

See datasheet for more information.